You will implement channelization, filtering, demodulation, and detection datapaths in HDL on RFSoC-class devices, working from reference models produced by the DSP team and delivering firmware that meets throughput and latency requirements on deployed hardware.

This is a design role, not a maintenance role. You will make architectural decisions about how a processing chain gets partitioned, where precision gets spent, and what gets pushed to software.

What you will do

HDL development

• Write synthesizable VHDL for high-throughput streaming DSP datapaths
• Implement digital down/up conversion, polyphase channelizers, FIR and CIC filter chains, NCOs, and demodulation logic
• Design and integrate AXI-Stream and AXI-Lite interfaces, DMA paths, and control/status register maps
• Partition designs across programmable logic and processing system on SoC targets

Verification

• Build and maintain self-checking testbenches with stimulus derived from DSP team reference models
• Perform bit-accurate comparison against golden models and drive discrepancies to root cause
• Maintain regression test coverage as the design evolves across baselines

Architecture and resource management

• Own timing closure, floorplanning, and clock domain crossing strategy
• Perform fixed-point precision analysis and manage the tradeoff between numerical fidelity and DSP slice consumption
• Track resource, power, and thermal budgets against platform constraints and raise the flag early when they will not close

Hardware bring-up and integration

• Bring up new board designs alongside the hardware team
• Debug in-system with integrated logic analyzers, external instrumentation, and captured signal injection
• Support integration and test events, including troubleshooting emulating field conditions

Minimum qualifications

• BS in Electrical Engineering, Computer Engineering, or related
• 5+ years of FPGA development with substantive DSP content (signal processing datapaths, not primarily glue logic or control state machines)
• Fluency in fixed-point arithmetic and its practical consequences
• Hands-on experience with Xilinx/AMD tooling (Vivado, Vitis) or equivalent
• Demonstrated ownership of timing closure on a nontrivial design

Preferred qualifications

• Direct RFSoC experience, including RF data converter configuration and calibration
• Experience with high-speed serial interfaces (JESD204, Aurora) and multi-gigabit data movement
• Familiarity with partial reconfiguration or multi-personality designs
• Embedded Linux and PetaLinux or Yocto exposure on Zynq-class parts
• Fluency in DDC/DUC, polyphase filterbanks, and AXI-Stream interfaces
• Active TS/SCI

Estimated Salary Range: $140,000-$245,000 per year

The salary range noted is intended as a general guide. Actual base salary offers from Xenon Innovations are determined based on several factors, including the position's scope and responsibilities, along with the candidate's experience, education, skill set, and prevailing market conditions. 

Xenon Innovations, Inc. is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, age, disability, genetic information, or protected veteran status.